1) Field of the Invention
The present invention relates to a technology for controlling coherency between a cache memory and a main memory in a multiprocessor system having an independent cache memory for each of a plurality of processors, by which a transaction between the cache memory and the main memory can be reduced and performance degradation of the multiprocessor system can be prevented.
2) Description of the Related Art
There are multiprocessor systems in which an independent cache is provided for each processor. In such multiprocessor systems the cache may be an integral part of the processor. Methods such as MESI protocol, speculative read, snoop cache, etc. have been conventionally employed in multiprocessor systems to effectively ensure coherency and thus enhance the performance.
The MESI protocol is a type of cache coherency protocol in which the memory system is managed by categorizing each line of the cache into one of the four statuses, namely, “Modified”, “Exclusive”, “Shared”, and “Invalid”. The MESI protocol unambiguously identifies the location of latest data, thus effectively ensuring coherency between each cache and the main memory (see, for example, Japanese Patent Laid-Open Publication No. 2002-24198).
In the speculative read method, the processor is queried and simultaneously a read request to read the main memory is also made. When a processor requests for data, each of the processors has to be queried for the requested data. This is done to ensure coherency of data. The read request to read the main memory is carried out only after a response is received from the processor. This results in significant latency (delay).
Therefore, by issuing a query to a processor and simultaneously issuing a speculative read request to read the main memory, the data speculatively read from the main memory is transmitted to the processor that made the read request, if the response for the processor suggests that the requested data is not available. Thus, the latency in fetching the data can be reduced by employing the speculative read method.
However, if a speculative read request is issued for every read request, the transaction between the cache and the main memory will go up significantly, resulting in degradation of the system performance. Therefore, a method that employs a snoop cache is adopted. In this method, a snoop cache is provided as an integral part of a memory system control apparatus which controls memory access. The snoop cache stores information pertaining to the lines of each cache memory.
The memory system control apparatus refers to the status of the snoop cache to gauge the status of each line of the cache of each processor without having to query the processors, thereby dispensing with speculative read requests (see, for example, Japanese Patent Laid-Open Publication No. H8-185359).
However, depending on the specification of the bus that connects the processors, the memory system control apparatus may not accurately gauge the transitions in the status of the cache of the processors. Referring to the snoop cache does not give the accurate status of the cache. This necessitates querying the processors.
To avoid increasing the latency in obtaining response from the processors, it becomes necessary to use speculative read request to read the main memory. However, since many speculative read requests are issued, the transaction between the cache and the main memory goes up significantly, thereby adversely affecting the system performance.